Future manycore processors will require energy-efficient, high throughput on-chip networks. Silicon photonics is a promising new technology which offers lower power, higher bandwidth density, and shorter latencies than electrical interconnects. In this paper we explore using photonics to implement large low-diameter non-blocking networks (e.g. global crossbars and Clos networks). Our analysis shows that for a 64-tile system our novel Clos implementations consume significantly less optical power, thermal tuning power, and area compared to global photonic crossbars over a range of photonic device parameters. Our simulation results indicate that a photonic Clos implementation can provide more uniform latency and throughput across a range of traffic patterns as compared to various electrical on-chip networks while consuming less power. These properties will help simplify parallel programming by allowing the programmer to ignore network topology during optimization.