To provide a well-balanced design in a power and area constrained system, and enable performance scaling with increase in number of cores per die, high-throughput energy-efficient on-chip networks have to be developed. In this paper we propose a cross-cut, level-transparent modeling approach that will enable rapid mapping of emerging interconnect technologies to the on-chip communication network performance for a variety of network topologies. We illustrate these concepts by a joint comparison of copper and carbon nanotube interconnect technologies at device, circuit and system level for example network topologies, showing that this level-transparent modeling approach is an efficient tool in determining a complete interconnect solution - from interconnect technology to network topology for a manycore system.