Call for Papers

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NOCS is the premier event dedicated to interdisciplinary research on on-chip communication technology, architecture, design methods and applications, bringing together scientists and engineers working on NoC innovations from inter-related research communities, including computer architecture, networking, circuits and systems, embedded systems, and design automation.

Original papers describing new and previously unpublished results are solicited on all aspects of NoC technology. Topics of interest include, but are not limited to:

  • Network architecture (topology, routing, arbitration, ...)
  • Network design for 3D stacked logic and memory
  • Mapping of applications onto NoCs
  • Power and energy issues
  • Timing, synchronous/asynchronous communication
  • NoC reliability issues
  • O/S support for NoCs
  • Metrics and benchmarks for NoCs
  • Multi/many-core workload characterization & evaluation
  • NoC network interface issues
  • Modeling, simulation, and synthesis of NoCs
  • NoC support for memory and cache access
  • NoC design methodologies and tools
  • NoC Quality of Service
  • NoCs for FPGAs and structured ASICs
  • NoC support for CMP/MPSoCs
  • Novel interconnect links/switches/routers
  • Optical & RF for on-chip/in-package interconnects
  • Signaling and circuit design for NoC links
  • Physical design of interconnect and NoC
  • Floorplan-aware NoC architecture optimization
  • Verification, debug & test of NoC
  • NoC case studies, application-specific NoC design
  • Programming models

Electronic paper submission requires a full paper, up to 10 double-column IEEE format pages, including figures and references. Papers will be evaluated by the program committee in a blind review process based on scientific merit, innovation, relevance, and presentation. Please see the paper submission instructions for details.

Proposals for tutorials, special sessions, panels are also invited. Please see the proposal submission instructions for details.

A special section related to the theme of the conference will be organized in collaboration with the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Important Dates

Abstract registration deadline January 23, 2009 (hard deadline, 11:59pm PST)
Full paper submission deadline January 30, 2009 (hard deadline, 11:59pm PST)
Proposals for tutorials, special sessions, and panels January 30, 2009
Notification of acceptance March 13, 2009
Final version due April 6, 2009
Advance registration deadline April 20, 2009
Hotel reservation deadline April 27, 2009
Symposium May 10-13, 2009

Sponsored by the IEEE Circuits and Systems Society, Council for EDA, ACM Special Interest Group on Computer Architecture (SIGARCH), ACM Special Interest Group on Embedded Systems (SIGBED), and ACM Special Interest Group on Design Automation (SIGDA).