Preliminary Program


Sunday, May 10, 2009
9:30 AM - 12:30 PM Tutorial 1: [Slides 1] [Slides 2] [Slides 3] [Slides 4]

The Elements of NoC
Israel Cidon, Avinoam Kolodny, Ran Ginosar
Technion, Israel

12:30 PM - 1:30 PM Lunch
1:30 PM - 3:30 PM Tutorial 2: [Slides]

RF-Interconnect and Application to NoC Designs
Frank Chang, Jason Cong, Glenn Reinman
UCLA

3:30 PM - 4:00 PM Break
4:00 PM - 6:00 PM Tutorial 3: [Slides]

Test of NoCs and NoC-based Systems-on-Chip
Erika Cota, Marcelo Lubaszewski
U. Federal Rio Grande do Sul, Brazil

6:30 PM - 8:30 PM Reception
 
Monday, May 11, 2009
8:00 AM - 8:30 AM Breakfast
8:30 AM - 8:45 AM Official Opening and Welcome:

General Chairs: Bill Lin and Partha Kundu
Program Chairs: Radu Marculescu and Axel Jantsch

8:45 AM - 9:45 AM Keynote 1: [Slides]

NOCs: It is About the Memory and the Programming Model
Ivo Bolsens, Sr. VP and CTO, Xilinx, Inc.

9:45 AM - 10:00 AM Break
10:00 AM - 12:00 NOON Session 1: Routing (Chair: Martti Forsell, VTT)

HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip
Rickard Holsmark1, Maurizio Palesi2, Shashi Kumar1, Andres Mejia3
1Jönköping University, Sweden, 2University of Catania, Italy, 3University Politecnica de Valencia, Spain
[Slides]

(*) Using Adaptive Routing to Compensate for Performance Heterogeneity
Yury Markovsky, Yatish Patel, John Wawrzynek
UC Berkeley
[Slides]

Fault-Tolerant Architecture and Deflection Routing for Degradable NoC Switches
Adan Kohler and Martin Radetzki
Universitaet Stuttgart
[Slides]

(S) Adaptive Stochastic Routing in Fault-tolerant On-chip Networks
Wei Song1, Doug Edwards1, Jose Nunez-Yanez2, Sohini Dasgupta1
1the University of Manchester, 2Bristol University
[Slides]

(S) Static Virtual Channel Allocation in Oblivious Routing
Keun Sup Shim1, Myong Hyon Cho1, Michel Kinsy1, Tina Wen1, Mieszko Lis1, G. Edward Suh2, Srinivas Devadas1
1MIT, 2Cornell
[Slides]

12 NOON - 1:30 PM Lunch
1:30 PM - 3:30 PM Session 2: Performance and Energy (Chair: Umit Ogras, Intel Corp)

Analysis of Worst-case Delay Bounds for Best-effort Communication in Wormhole Networks on Chip
Yue Qian1, Zhonghai Lu2, Wenhua Dou1
1School of Computer Science, National Univ. of Defense Tech., China, 2Dept. of Electronic, Computer and Software Systems, Royal Institute of Technology (KTH), Sweden
[Slides]

Lookahead-Based Adaptive Voltage Scheme for Energy-Efficient On-Chip Interconnect Links
Bo Fu, David Wolpert, Paul Ampadu
University of Rochester

Recursive Partitioning Multicast: A Bandwidth-Efficient Routing for On-Chip Networks
Lei Wang, Yuho Jin, Hyungjun Kim, Eun Jung Kim
Texas A&M University
[Slides]

(S) Analytical Modeling and Evaluation of On-Chip Interconnects Using Network Calculus
Mohamed Bakhouya1, Suboh Suboh2, Jaafar Gaber1, Tarek El-Ghazawi2
1University of Technology of Belfort Montbeliard, 2George Washington University
[Slides]

(S) Energy Efficient Application Mapping to NoC Processing Elements Operating at Multiple Voltage Levels
Pavel Ghosh1, Arunabha Sen2, Alexander Hall3
1Computer Science and Engineering Department, Arizona State University, 2Computer Science and Engineering Department, Arizona State University, 3Department of EECS, UC Berkeley
[Slides]

3:30 PM - 4:30 PM Session 3: Poster Session

The Design of a Latency Constrained, Power Optimized NoC for a 4G SoC
Rudy Beraha1, Isask'har Walter2, Israel Cidon2, Avinoam Kolodny2
1Qualcomm, 2Technion - Israel Institute of Technology

Performance Evaluation of NoC Architectures for Parallel Workloads
Henrique Freitas, Marco Alves, Lucas Schnorr, Philippe Navaux
Universidade Federal do Rio Grande do Sul
[Slides]

Packet-Level Static Timing Analysis for NoCs
Evgeni Krimer1, Mattan Erez1, Isaac Keslassy2, Avinoam Kolodny2, Isask'har Walter2
1University of Texas at Austin, 2Technion - Israel Institute of Technology

Increasing NoC Power Estimation Accuracy through a Rate-Based Model
Guilherme Guindani, Cezar Reinbrecht, Thiago da Rosa, Fernando Moraes
PUCRS
[Slides]

On-Chip Photonic Interconnects for Scalable Multi-core Architectures
Avinash Kodi1, Randy Morris1, Ahmed Louri2, Xiang Zhang2
1Ohio University, 2University of Arizona

A Modeling and Exploration Framework for Interconnect Network Design in the Nanometer Era
Ajay Joshi, Fred Chen, Vladimir Stojanovic
Massachusetts Institute of Technology
[Slides]

Power Reduction Through Physical Placement of Asynchronous Routers
Daniel Gebhardt and Kenneth Stevens
University of Utah

4:30 PM - 6:00 PM Session 4: Special Session (Chair: Marcelo Lubaszewski, U. Federal Rio Grande do Sul)

Networks-on-Chip in Emerging Interconnect Paradigms: Advantages And Challenges

I. NoC design using 3D Stacking Technology
Yuan Xie
Pennsylvania State University

II. Photonic Interconnection Networks for Multi-Core Platforms
Luca Carloni
Columbia University

III. On-chip Wireless Communication Network for Multi-Core Systems
Partha Pande
Washington State University

 
Tuesday, May 12, 2009
8:00 AM - 8:30 AM Breakfast
8:45 AM - 9:45 AM Keynote 2: [Slides]

NoC's at the Center of Chip Architecture: Urgent Needs (Today) and What They Must Become (Future)
Andrew Chien, VP and Director of Research, Intel, Corp.

9:45 AM - 10:00 AM Break
10:00 AM - 12:00 NOON Session 5: 3D and Optical Networks (Chair: Partha Pande, Washington State)

Analysis of Photonic Networks for a Chip Multi-Processor Using Scientific Applications
Gilbert Hendry1, Aleksandr Biberman1, Johnnie Chan1, Shoaib Kamil2, Benjamin Lee1, Marghoob Mohiyuddin2, Keren Bergman1, Luca Carloni1, Leonid Oliker3, John Shalf3
1Columbia University, 2University of California, Berkeley, 3Lawrence Berkeley National Laboratory
[Slides]

Scalability of Network-on-Chip Communication Architecture for 3-D Meshes
Awet Yemane Weldezion1, Matt Grange2, Dinesh Pamunuwa2, Zhonghai Lu1, Axel Jantsch1, Roshan Weerasekera2, Hannu Tenhunen1
1KTH Royal Institute of Technology, 2Lancaster University
[Slides]

(*) Silicon-Photonic Clos Networks for Global On-Chip Communication
Ajay Joshi1, Christopher Batten1, Yong-Jin Kwon2, Scott Beamer2, Imran Shamim1, Krste Asanovic1, Vladimir Stojanovic1
1Massachusetts Institute of Technology, 2University of California, Berkeley
[Slides]

Contention-Free on-Chip Routing of Optical Packets
Somayyeh Koohi and Shaahin Hessabi
Computer Engineering Department, Sharif University of Technology

12 NOON - 1:30 PM Lunch (Bandar Restaurant: 845 4th Ave., San Diego, CA)

1:30 PM - 3:30 PM Session 6: Network Architecture (Chair: Martin Radetzki, Univ. of Stuttgart)

Connection-Centric Network for Spiking Neural Networks
Robin Emery, Alex Yakovlev, Graeme Chester
Newcastle University, UK

A Communication and Configuration Controller for NoC-based Reconfigurable Data Flow Architecture
Fabien Clermidy, Romain Lemaire, Yvain Thonnart, Pascal Vivet
CEA-LETI

Configurable Emulated Shared Memory Architecture for general purpose MP-SOCs and NOC regions
Martti Forsell
VTT
[Slides]

Best of Both Worlds: A Bus-Enhanced NoC (BENoC)
Ran Manevich, Isask'har Walter, Israel Cidon, Avinoam Kolodny
Technion - Israel Insitute of Technology
[Slides]

3:30 PM - 4:00 PM Break
4:00 PM - 5:30 PM Session 7: Flow Oriented Techniques (Chair: Avinoam Kolodny, Technion)

Flow-Aware Allocation for On-Chip Networks
Arnab Banerjee and Simon Moore
Computer Laboratory, University of Cambridge
[Slides]

CTC: a Novel End To End Flow Control Protocol for SoC Architectures
Nicola Concer1, Luciano Bononi1, Michaël Soulié2, Riccardo Locatelli2, Luca Carloni3
1Bologna University, 2ST Microelectronics, 3Columbia University
[Slides]

Performance and Power Efficient On-Chip Communication Using Adaptive Virtual Point-to-Point Connections
Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol
Computer Engineering Department, Sharif University of Technology
[Slides]

6:30 PM - 8:30 PM Banquet

Keynote 3 (Banquet Talk): [Slides]

Digital Space
Anant Agarwal, MIT and CTO at Tilera Corp.

 
Wednesday, May 13, 2009
8:00 AM - 8:30 AM Breakfast
8:30 AM - 10:30 AM Session 8: Synchronization and Flow Control (Chair: Luca Carloni, Columbia University)

A GALS Many-Core Heterogeneous DSP Platform with Source-Synchronous On-Chip Interconnection Network
Anh Tran, Dean Truong, Bevan Baas
University of California - Davis
[Slides]

A Modular Synchronizing FIFO for NoCs
Tarik Ono1 and Mark Greenstreet2
1Sun Microsystems, 2University of British Columbia
[Slides]

Estimating Reliability and Throughput of Source-synchronous Wave-pipelined Interconnect
Paul Teehan, Mark Greenstreet, Guy Lemieux
University of British Columbia
[Slides]

(S) Comparing Tightly and Loosely Coupled Mesochronous Synchronizers in a NoC Switch Architecture
Daniele Ludovici1, Alessandro Strano2, Davide Bertozzi2, Georgi Gaydadjiev1, Luca Benini3
1TUDelft, 2University of Ferrara, 3University of Bologna
[Slides]

(S) Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers
Young Hoon Kang, Taek-Jun Kwon, Jeff Draper
University of Southern California / Information Sciences Institute
[Slides]

10:30 AM - 11:00 AM Break
11:00 AM - 12:30 PM Session 9: Links and Channels (Chair: Paul Ampadu, Rochester University)

(*) Diagnosis of Interconnect Shorts in Mesh NoCs
Marcos Hervé, Érika Cota, Fernanda Kastensmidt, Marcelo Lubaszewski
UFRGS Federal University
[Slides]

(*) BiNoC: A Bidirectional NoC Architecture with Dynamic Self-Reconfigurable Channel
Ying-Cherng Lan1, Shih-Hsin Lo1, Yueh-Chi Lin1, Yu-Hen Hu2, Sao-Jie Chen1
1National Taiwan University, 2University of Wisconsin
[Slides]

Exploring Concentration and Channel Slicing in On-Chip Network Router
Prabhat Kumar, Yan Pan, John Kim, Gokhan Memik, Alok Choudhary
Northwestern University
[Slides]

12:30 PM - 2:00 PM Lunch (Athens Market Taverna: 109 West F Street, San Diego, CA)

2:00 PM - 3:15 PM Session 10: Panel Session (Moderator: Radu Marculescu, CMU)

What Issues Will Have The Biggest Impact on Future NoCs?
[Slides] Krste Asanovic (UC Berkeley)
[Slides] Chita Das (NSF/Penn State)
[Slides] Ran Ginosar (Technion)
[Slides] Michael Kishinevsky (Intel Corp) [Slides]

3:15 PM - 3:30 PM Conclusion
Legend:

(S) ... Short paper

(*) ... Best paper candidate