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Title: RF-Interconnect and Application to NoC Designs
Speakers:
Frank Chang1, Jason Cong2, and Glenn Reinman2
1Electrical Engineering, UCLA,
2Computer Science, UCLA
Abstract:
The first part of this tutorial will cover the rationale, the algorithm, the CMOS circuit design and exemplary implementations of RF-interconnect for inter-core communication applications. The second part of the tutorial covers the design and optimization problems of NoC with RF-interconnects, such as RF-I short-cut addition and deadline avoidance. Finally, we present the implication of RF-interconnect enabled NoC, in terms of performance, power, multi-cast support, etc.
Speaker Bios:
Frank Chang is the Wintek Chair Professor at the Electrical Engineering Department of UCLA. He was the inventor of the multiband, reconfigurable RF/Wireless-Interconnects, based on FDMA/CDMA multiple access algorithms, for ChipMulti-Processor (CMP) inter-core and for CPU-to-Memory inter-chip and inter-board communications. He was elected to the US National Academy of Engineering in 2008 for the development and commercialization of RF power amplifiers and integrated circuits for wireless communications. He is also a Fellow of IEEE and received IEEE David Sarnoff Award in 2006. His recent paper co-authored with Jason Cong and Glenn Reinman "CMP Network-on-chip Overlaid with Multiband RF-Interconnect" was selected for the Best Paper Award in 2008 IEEE International Symposium on High-Performance Computer Architecture (HPCA).
Jason Cong received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Chancellor's Professor at the Computer Science Department of University of California, Los Angeles, and a co-director of the VLSI CAD Laboratory. He also served as the department chair from 2005 to 2008. Dr. Cong's research interests include computer-aided design of VLSI circuits and systems, design and synthesis of system-on-a-chip, programmable systems, novel computer architectures, nano-systems, and highly scalable algorithms. He has published over 280 research papers and led over 30 research projects in these areas. Dr. Cong received a number of awards and recognitions, including the Ross J. Martin Award for Excellence in Research from the University of Illinois at Urbana-Champaign in 1989, the NSF Young Investigator Award in 1993, the Northrop Outstanding Junior Faculty Research Award from UCLA in 1993, the ACM/SIGDA Meritorious Service Award in 1998, and the SRC Technical Excellence Award in 2000. He also received four Best Paper Awards selected for the 1995 IEEE Trans. on CAD, the 2005 International Symposium on Physical Design (ISPD), the 2005 ACM Transaction on Design Automation of Electronic Systems, and the 2008 International Symposium on High Performance Computer Architecture (HPCA), respectively. He was elected to an IEEE Fellow in 2000 and ACM Fellow in 2008.
Glenn Reinman is an Associate Professor in the Department of Computer Science at University of California, Los Angeles. He received his Ph.D. and M.S. in Computer Science at the University of California, San Diego in 2001 with a dissertation on fetch optimizations for aggressive out-of-order superscalar processors. He received a B.S. in Computer Science and Engineering from the Massachusetts Institute of Technology in 1996. Glenn was awarded an NSF CAREER grant in 2001 titled The Evaluation and Design of an Scalable, High-Performance, and Energy-Efficient Microprocessor Architecture. He has also received the Northrop Grumman Excellence in Teaching Award in 2004 and was named Professor of the Year by the undergraduate chapter of the Engineering Society of the University of California Los Angeles in 2006. His research interests are in the area of computer architecture and compiler design, particularly for chip multiprocessor architectures, including the discovery and exploitation of thread, instruction, and memory level parallelism, branch prediction and instruction fetch, cache design and prefetching, load speculation, and profile-guided optimization.